This application claims the priority of Korean Patent Application No. 2002-47584, filed on Aug. 12, 2002 in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device, such as a dynamic random access memory (DRAM), and system that require refresh operations for storage of data.
2. Description of the Related Art
Static random access memory (SRAM) is required in a personal handheld phone system such as a cellular phone. However, since there is an integration limit for SRAM, DRAM has gradually replaced SRAM. Use of DRAM has been disclosed in U.S. Pat. Nos. (hereinafter, referred to as U.S. Pat. Nos.) 6,275,437; 4,984,208; and 5,999,474.
Unlike SRAM, DRAM requires refresh operations for storage of data and operational features of the DRAM are also largely affected by the refresh operations. To solve this problem, U.S. Pat. No. 5,999,474 suggested an apparatus and method for hiding the refresh of a semiconductor memory, the apparatus having a multi-bank structure and cache memory.
U.S. Pat. No. 6,275,437 is directed to refresh-type memory with zero write-recovery time and no maximum cycle time. In this case, both a word line for refresh operations and a word line for normal access are realized in response to an external command, thereby hiding refresh operations. In detail, performing refresh operations with an internal refresh timer allows a memory controller to access memory regardless of the refresh operations.
In a case where a cache memory is used to hide refresh operations, as described in U.S. Pat. No. 5,999,474, great portions of a memory device are occupied by the cache memory. Also, a refresh failure may be caused when a cache memory miss continuously occurs due to numerous attempts to externally access a certain bank. Therefore, it is difficult to completely prevent the occurrence of a refresh fail when considering that an access to cache memory depends on a statistical estimation.
As disclosed in U.S. Pat. Nos. 6,275,437 and 4,984,208, if both a row cycle operation and a normal row cycle operation are performed for every normal access, i.e., read/write access, an increase in row cycle time is unavoidable. As a result, a cycle time for read/write operations is longer than the refresh cycle time of a general DRAM. To solve this problem, U.S. Pat. No. 6,275,437 suggests the use of a write buffer, but a cycle time spent on read/write operations is still increased.
FIG. 1 is a block diagram of a conventional semiconductor memory system 100 having a memory device 120 and a conventional memory controller 110. Refresh operations of the memory device 120 are entirely controlled by the memory controller 110. In detail, the memory controller 110 includes a refresh counting unit and periodically outputs a refresh command based on a data retention time specification. Thus, sending read/write commands to the memory device 120 is withheld in the memory controller 110 during refresh operations.